The present invent-on relates to a semiconductor device and a method for fabricating the same, more specifically to a high-integration DRAM and a method for fabricating the same.
The present invention can realize a large capacitor and a micronized memory while securing an alignment allowance in a lithography step and electric isolation.
With reference to FIGS. 3A and 3B, a conventional semiconductor device and a method for fabricating the same will be explained.
A field oxide film 2 for defining a device region is formed on a semiconductor substrate 1. A gate 4 of memory cell transistor is formed through a gate oxide film 3 in the device region defined by the field oxide film 2. A part of the gate 4 is extended on the field oxide film 2. An insulation film 5 is formed on the side walls and the upper surface of the gate 4. A silicon nitride (Si3N4) film 6 which function as an etching stopper and an inter-layer insulation film 12 are formed on the semiconductor substrate 1 having memory cell transistor. A through-hole is formed through these films down to the semiconductor substrate 1. A storage electrode 9 of a capacitor connected to the semiconductor substrate 1 is formed on the inside wall and the bottom of the through-hole. An opposed electrode 11 of the capacitor is formed through a dielectric film 10 on the surface of the storage electrode 9.
In the exemplified conventional semiconductor device, the side wall of the through-hole for the capacitor contact is vertical or tapered. In such capacitor, in a case that the through-hole ha s a large diameter for a larger capacitance, the opening is subjected to restrictions for an alignment allowance for a bit line contact and for electric isolation.
In a case that a hole diameter and a disalignment are large, as shown in FIG. 3A, the field oxide film 2 is adversely dug even though the contact is formed in self-alignment with the gate 4 to reluctantly form a projection in the capacitor, with a resultant problem that an electric field tends to be concentrate d to cause dielectric breakdown of the dielectric film 10. Increase of a hole diameter is restricted.
In a case that, as shown in FIG. 3B, the contact is formed only by an optical alignment, a hole diameter must be smaller because the storage electrode of the capacitor tends to short-circuit with the gate electrode.
Accordingly, in a case that the capacitor has such configuration, it is restricted to simply increase a hole diameter for a larger capacitance. As means for effectively omitting such restriction to the opening, the bit line contact is formed before, and then the capacitor is formed. A problem with this means is fabrication step increase.
An object of the present invention is to provide a larger capacitance while the requirements of alignment allowance for the alignment of an opening for a capacitor contact and a bit line contact, and of electric isolation from an adjacent conducting films.
The above-described object is achieved by a semiconductor device comprising: a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate: an insulation film covering a top of the MOSFET, a through-hole opened on one of the impurity diffused regions being formed in the insulation film; and a capacitor formed at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof.
The above-described object is also achieved by a semiconductor device comprising: a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate: an insulation film covering a top of the MOSFET, a through-hole opened on one of the impurity diffused regions being formed in the insulation film; and a capacitor formed at least a part of an inside of the through-hole, the through-hole having a larger diameter at an intermediate part thereof between a surface thereof and a bottom thereof than at the surface and the bottom thereof.
The above-described object is also achieved by a method for fabricating a semiconductor device comprising: a MOSFET forming step of forming on a semiconductor substrate a MOSFET including a gate and a pair of impurity diffused regions on both sides of the gate; an insulation film forming step of forming an insulation film for covering the MOSFET; a through-hole forming step of forming in the insulation film a through-hole having a larger diameter inside than at a surface thereof, the through-hole being opened on one of the impurity diffused regions; and a capacitor forming step of forming a capacitor at least a part of an inside of the through-hole.
The above-described object is also achieved by a method for fabricating a semiconductor device comprising: a MOSFET forming step of forming on a semiconductor substrate a MOSFET including a gate and a pair of impurity diffused regions on both sides of the gate; an insulation film forming step of forming an insulation film for covering the MOSFET; a through-hole forming step of forming in the insulation film a through-hole having a larger diameter at an intermediate part between a surface thereof and a bottom thereof than the surface and the bottom thereof, the through-hole being opened on one of the impurity diffused regions; and a capacitor forming step of forming a capacitor at least a part of an inside of the through-hole.
The above-described object is also achieved by a method for fabricating a semiconductor device comprising: a MOSFET forming step of forming on a semiconductor substrate a MOSFET including a gate and a pair of impurity diffused regions on both sides of the gate; an insulation film forming step of forming a plurality of insulation films being laminated for covering the MOSFET; a through-hole forming step of forming in the insulation films a through-hole having a larger diameter inside than at a surface thereof, the through-hole being opened on one of the impurity diffused regions; and a capacitor forming step of forming a capacitor at least a part of an inside of the through-hole.
In the above-described method for fabricating the semiconductor device, it is preferable that the insulation film forming step includes a step of forming a first insulation film, and a step of forming on the first insulation film a second insulation film having etching characteristics different from those of the first insulation film; and the through-hole forming step includes a step of forming in the first insulation film and the second insulation film the through-hole having substantially the same opening diameter, and a step of retreating the first insulation film inside the through-hole by the use of an etchant having a higher etching rate with respect to the first insulation film than with respect to the second insulation film.
The above-described object is also achieved by a method for fabricating a semiconductor device comprising: a MOSFET forming step of forming on a semiconductor substrate a MOSFET including a gate and a pair of impurity diffused regions on both sides of the gate; an insulation film forming step of forming a plurality of insulation films being laminated for covering the MOSFET; a through-hole forming step of forming in the insulation films a through-hole having a larger diameter at an intermediate part between a surface thereof and a bottom thereof than the surface and the bottom thereof, the through-hole being opened on one of the impurity diffused regions; and a capacitor forming step of forming a capacitor at at least a part of an inside of the through-hole.
In the above-described method for fabricating the semiconductor device, it is preferable that the insulation film forming step includes a step of forming a first insulation film, a step of forming on the first insulation film a second insulation film having etching characteristics different from those of the first insulation film, and a step of forming on the second insulation film a third insulation film having etching characteristics different from those of the second insulation film; and the through-hole forming step includes a step of forming in the first insulation film, the second insulation film and the third insulation film the through-hole having substantially the same opening diameter, and a step of retreating the second insulation film inside the through-hole s by the use of an etchant having a higher etching rate with respect to the s econd insulation film than with respect to the first and the third insulation film.
In the above-described method for fabricating the semiconductor device, it is preferable that the insulation film forming step includes a step of forming a first insulation film, a step of forming on the first insulation film a second insulation film having etching characteristics different from those of the first insulation film, and a step of forming on the second insulation film a third insulation film having etching characteristics different from those of the second insulation film; and the through-hole forming step includes a step of etching the second and the third insulation films by the use of an etchant which has a higher etching rate with respect to the second insulation film than with respect to the third insulation film and substantially anisotropically contains an isotropic component, and a step of isotropically etching the first insulation film by the use of an etchant having a higher etching rate with respect to the first insulation film than with respect to the second insulation film.
In the above-described method for fabricating the semiconductor device, it is preferable that the etchant for etching the first insulation film has a higher etching rate with respect to the second insulation film than with respect to the third insulation film.
In the above-described method for fabricating the semiconductor device, it is preferable that the first insulation film is a silicon nitride film; the second insulation film is a silicon oxide film containing boron and/or phosphorus: the third insulation film is a non-doped silicon oxide film.